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RT9241A/b ds9241ab-01 october 2002 www.richtek.com 1 two-phase dc/dc controller for cpu core power supply general description the RT9241A/b is a two-phase buck dc/dc controller integrated with all control functions for high performance processor vrm. the RT9241A/b drives 2 buck switching stages operating in 180 degree phase shift. the two-phase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. the high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9241A/b regulates both easily set voltage and current loops. precise current sharing for power stage is achieved by differential input current sense and processing circuit. the settings of current sense, droop tuning and over current protection are independent to compensation circuit of voltage loop. the feature greatly facilitat es the flexibility of cpu power supply design and tuning. the RT9241A/b uses a 5-bit dac of 1.1v to 1.85v (25mv/step) output with load current droop compensation to meet the strict vrm transient requirement. the ic monitors the vcore voltage for pgood and over voltage protection. soft start, over current protection and programmable under voltage lockout are also provided to assure the safety of microprocessor and power system. ordering information RT9241A/b features two-phase power conversion vrm 9.0 dac output with active droop compensation for fast load transient precise channel current sharing with differential sense input hiccup mode over current protection programmable under voltage lockout and soft start high ripple frequency, (channel frequency times channel number) 100khz version (rt9241b) for lower switching loss applications power supply for server and workstation power supply for high current microprocessor pin configurations part number pin configurations RT9241A/b cs (plastic sop-20) top view 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 12 11 vid3 vid2 vid1 vid0 comp fb adj vsen vid4 dvd ss vdd pgood isp1 pwm1 pwm2 isp2 isn1 isn2 gnd operating temperature range c: commercial standard package type s : sop-20 operating frequency version a : 200khz b : 100khz
RT9241A/b www.richtek.com ds9241ab-01 october 2002 2 absolute maximum ratings supply voltage 7v input, output or i/o voltage gnd-0.3v ~ v dd +0.3v power dissipation, p d @ t a = 25 c sop-20 0.625w package thermal resistance sop-20, ja 110 c /w ambient temperature range 0 c ~ 70 c junction temperature range 0 c ~ 125 c storage temperature range -40 c ~ 150 c lead temperature (soldering, 10 sec.) 260 c electrical characteristics (v dd = 5v, gnd = 0v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max units v dd supply current nominal supply current i dd pwm 1,2 open -- 4 10 ma power-on reset v dd rising threshold 4.2 4.35 4.6 v v dd falling threshold -- 3.85 -- v hysteresis 0.2 0.6 -- v v dvd rising trip threshold 1.19 1.25 1.31 v oscillator RT9241A 170 200 230 frequency rt9241b for each phase 85 100 115 khz ramp amplitude -- 1.7 -- v ramp valley 1.0 1.3 -- v maximum on time of each channel 70 75 80 % reference and dac dacout voltage accuracy -1.0 -- +1.0 % dac (vid0-vid4) input low voltage -- -- 0.8 v dac (vid0-vid4) input high voltage 2.0 -- -- v dac (vid0-vid4) bias current 20 28 36 a pwm controller error amplifier dc gain -- 85 -- db bandwidth -- 10 -- mhz slew rate c l = 10pf -- 5 -- v/ s to be continued
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 3 parameter symbol test conditions min typ max units current sense gm amplifier isp 1,2 full scale source current 50 -- -- a isp 1,2 current for ocp 70 75 -- a protection ss current v ss = 1v 8 13 18 a over-voltage trip (vsen/dacout) 118 122 126 % power good upper threshold (vsen/dacout) vsen rising 106 110 114 % lower threshold (vsen/dacout) vsen rising 86 90 94 % function block diagram + _ cur r ent balance processor + _ + _ pwm logic & driver pwm logic & driver oscillator + _ current limit ov p, pgood por logic + _ + _ 92% vdac 120% vdac po w er on re s e t droop control ss contr ol da c pw m1 pw m2 is p1 is n1 is p2 is n2 dv d inh inh inh vdd pg oo d vid1 vid0 vid2 vid3 vid4 vsen adj gnd fb co mp ss cs1 cs2 pw m c p pw m c p + _ 108% vdac ea + _ + _ + _ cur r ent balance processor + _ + _ + _ + _ pwm logic & driver pwm logic & driver pwm logic & driver pwm logic & driver oscillator oscillator + _ + _ current limit current limit ov p, pgood por logic ov p, pgood por logic + _ + _ + _ 92% vdac 120% vdac 120% vdac po w er on re s e t po w er on re s e t droop control droop control ss contr ol ss contr ol da c da c pw m1 pw m2 is p1 is n1 is p2 is n2 dv d inh inh inh vdd pg oo d vid1 vid0 vid2 vid3 vid4 vsen adj gnd fb co mp ss cs1 cs2 pw m c p pw m c p + _ + _ 108% vdac 108% vdac ea + _ + _
RT9241A/b www.richtek.com ds9241ab-01 october 2002 4 table 1 output voltage program pin name vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 1 1 1 1 1 off 1 1 1 1 0 1.100v 1 1 1 0 1 1.125v 1 1 1 0 0 1.150v 1 1 0 1 1 1.175v 1 1 0 1 0 1.200v 1 1 0 0 1 1.225v 1 1 0 0 0 1.250v 1 0 1 1 1 1.275v 1 0 1 1 0 1.300v 1 0 1 0 1 1.325v 1 0 1 0 0 1.350v 1 0 0 1 1 1.375v 1 0 0 1 0 1.400v 1 0 0 0 1 1.425v 1 0 0 0 0 1.450v 0 1 1 1 1 1.475v 0 1 1 1 0 1.500v 0 1 1 0 1 1.525v 0 1 1 0 0 1.550v 0 1 0 1 1 1.575v 0 1 0 1 0 1.600v 0 1 0 0 1 1.625v 0 1 0 0 0 1.650v 0 0 1 1 1 1.675v 0 0 1 1 0 1.700v 0 0 1 0 1 1.725v 0 0 1 0 0 1.750v 0 0 0 1 1 1.775v 0 0 0 1 0 1.800v 0 0 0 0 1 1.825v 0 0 0 0 0 1.850v note: (1) 0:connected to gnd (2) 1:open
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 5 typical application circuit 1 2 3 4 5 6 7 8 13 14 9 10 15 11 18 17 16 12 20 19 vid4 vid3 vid2 vid1 vid0 comp fb adj dvd vsen ss isn2 isp2 isn1 pwm2 pwm1 isp1 pgood vdd RT9241A pgood +5v typical 12v pwm pvcc vcc boot ugate phase lgate gnd 1 2 3 4 5 6 7 8 rt9600 c 4 1 f c 3 1 f c 1 1 f c 2 1000 f/16v q 1 phb83n03lt q 2 phb95n03lt l2 2 h c 5 1500 f c 6 1500 f r1 2.4k r2 2.4k typical 12v pwm pvcc vcc boot ugate phase lgate gnd 1 2 3 4 5 6 7 8 rt9600 c 13 1 f c 11 1 f c 8 1 f c 9 1000 f q 3 phb83n03lt q 4 phb95n03lt l3 2 h c 15 1500 f c 16 1500 f r10 2.4k r13 2.4k 12v vid4 vid3 vid2 vid1 vid0 c 17 0.1 f r 14 2.4k r 12 13k r 9 1k r 5 2.4k r 8 c 14 r 7 c 10 6.6nf r 6 24k c 12 33pf c 7 1 f r 3 10k l1 1 h 12v v core 0.01 f 0.01 f gnd r 15 +5v 1 2 3 4 5 6 7 8 13 14 9 10 15 11 18 17 16 12 20 19 vid4 vid3 vid2 vid1 vid0 comp fb adj dvd vsen ss isn2 isp2 isn1 pwm2 pwm1 isp1 pgood vdd RT9241A pgood +5v typical 12v pwm pvcc vcc boot ugate phase lgate gnd 1 2 3 4 5 6 7 8 rt9600 c 4 1 f c 3 1 f c 1 1 f c 2 1000 f/16v q 1 phb83n03lt q 2 phb95n03lt l2 2 h c 5 1500 f c 6 1500 f r1 2.4k r2 2.4k typical 12v pwm pvcc vcc boot ugate phase lgate gnd 1 2 3 4 5 6 7 8 rt9600 c 13 1 f c 11 1 f c 8 1 f c 9 1000 f q 3 phb83n03lt q 4 phb95n03lt l3 2 h c 15 1500 f c 16 1500 f r10 2.4k r13 2.4k 12v vid4 vid3 vid2 vid1 vid0 c 17 0.1 f r 14 2.4k r 12 13k r 9 1k r 5 2.4k r 8 c 14 r 7 c 10 6.6nf r 6 24k c 12 33pf c 7 1 f r 3 10k l1 1 h 12v v core 0.01 f 0.01 f gnd r 15 +5v
RT9241A/b www.richtek.com ds9241ab-01 october 2002 6 1 2 3 4 5 6 7 8 9 10 15 11 18 17 16 12 20 19 vid4 vid3 vid2 vid1 vid0 comp fb adj dvd ss isn2 isp2 isn1 pwm2 pwm1 isp1 pgood vdd RT9241A pgood +5v 1 f 1000 f phb83n03lt 3k 12v vid4 vid3 vid2 vid1 vid0 0.1 f 2.4k 13k 2.4k 2.4k 24k 33pf 1 f 10k 1.2 h 11 12 13 4 9 8 7 10 14 boot1 ugate1 phase1 lgate 1 ugate2 phase2 lgate 2 boot2 pgnd gnd pwm1 pwm2 pvcc vcc 5 1 2 3 6 14 vsen 13 gnd 12v 12v 3k 3k 3k 10 1 f 2 h phb95n03lt 1500 f 1000 f 1 f 2 h 1500 f 1 f rt9602 +5v v core phb83n03lt phb95n03lt 1 f 6.6nf 0.01 f 0.01 f 1 2 3 4 5 6 7 8 9 10 15 11 18 17 16 12 20 19 vid4 vid3 vid2 vid1 vid0 comp fb adj dvd ss isn2 isp2 isn1 pwm2 pwm1 isp1 pgood vdd RT9241A pgood +5v 1 f 1000 f phb83n03lt 3k 12v vid4 vid3 vid2 vid1 vid0 0.1 f 2.4k 13k 2.4k 2.4k 24k 33pf 1 f 10k 1.2 h 11 12 13 4 9 8 7 10 14 boot1 ugate1 phase1 lgate 1 ugate2 phase2 lgate 2 boot2 pgnd gnd pwm1 pwm2 pvcc vcc 5 1 2 3 6 14 vsen 13 gnd 12v 12v 3k 3k 3k 10 1 f 2 h phb95n03lt 1500 f 1000 f 1 f 2 h 1500 f 1 f rt9602 +5v v core phb83n03lt phb95n03lt 1 f 6.6nf 0.01 f 0.01 f
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 7 the hysteresis of v dd 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 123456 v dd (v) v core (v) the hysteresis of v dvd 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.9 1 1.1 1.2 1.3 1.4 1.5 v dvd (v) v core (v) typical operating characteristics pwm1 pwm2 v ss i out time (25ms/div) 20a/div) over current protection at power-up pwm1 pwm2 v ss i out time (25ms/div) 20a/div) over current protection at steady state pwm1 pwm2 i l1 i l2 time (5 s/div) current sharing between two phases i l1 i l2 pwm1 pwm2 i l1 i l2 time (5 s/div) two-phase converter without current sharing i l1 i l2
RT9241A/b www.richtek.com ds9241ab-01 october 2002 8 functional pin description vid4, vid3, vid2, vid1 and vid0 ( pin1,2,3,4,5) dac voltage identification inputs for vrm9.0. these pins are ttl-compatible and internally pulled to vdd if left open. comp (pin 6) output of the error amp lifier and input of the pwm comparator. fb (pin 7) inverting input of the internal error amplifier. adj (pin 8) current sense output for active droop adjust. connect a resistor from this pin to gnd to set the amount of load droop. this pin should not be opened. dvd (pin 9) programmable power uvlo detection input. trip threshold = 1.25v at v dvd rising ss (pin 10) connect this ss pin to gnd with a capacitor to set the start time interval. pull this pin below 1v(ramp valley of saw-tooth wave in pulse width modulator) to shutdown the converter output. isn1 (pin 12), isn2 (pin 11) current sense inputs from the individual converter channel?s sense component gnd nodes. gnd (pin 13) ground for the ic. vsen (pin 14) power good and over voltage monitor input. connect to the microprocessor-core voltage. isp1 (pin 18), isp2 (pin 15) current sense inputs for individual converter channels. tie this pin to the component sense node. pwm1 (pin 17), pwm2 (pin 16) pwm outputs for each driven channel. connect these pins to the pwm input of the mosfet driver. pgood (pin 19) power good open-drain output. vdd (pin 20) ic power supply. connect th is pin to a 5v supply.
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 9 simplified block diagram control loops for a two phase converter current balance processor + _ + _ pwm logic & driver pwm logic & driver + _ + _ + _ droop control ss control isp1 isn1 isp2 isn2 vdac gnd cs1 cs2 pwmcp pwmcp ea rt9600 rt9600 v in v in c out r load pwm1 pwm2 fb adj comp ss voltage loop current loop current balance processor + _ + _ + _ + _ pwm logic & driver pwm logic & driver pwm logic & driver pwm logic & driver + _ + _ + _ + _ + _ droop control droop control ss control ss control isp1 isn1 isp2 isn2 vdac gnd cs1 cs2 pwmcp pwmcp ea rt9600 rt9600 rt9600 rt9600 v in v in c out r load pwm1 pwm2 fb adj comp ss voltage loop current loop
RT9241A/b www.richtek.com ds9241ab-01 october 2002 10 operation RT9241A/b is a two-phase dc/dc controller that precisely regulates cpu core voltage and balances the current of different power channels. the converter consists of RT9241A/b and its companion mosfet driver provide high quality cpu power and all protection function to meet the requirement of modern vrm. voltage control the reference of v core is provided by a 5-bit dac of vrm9.0 specification. control loop consists of error amplifier, two-phase pulse width modulator, driver and power components. like conventional voltage mode pwm controller, the output voltage is locked at the v ref of error amplifier and t he error signal is used as the control signal v c of pulse width modulator. the pwm signals of different channels are generated by comparison of ea output and split-phase saw-tooth wave. power stage transforms v in to output by pwm signal on-time ratio. current balance RT9241A/b senses the current of low side mosfet in each synchronous rectifier when it is conducting for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the r ds(on) of the low side mosfet) to current signal into internal balance circuit. the current balance circuit sums and averages the current signals then produces the balancing signals injected to pulse width modulator. if the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. load droop the sensed power channel current signals regulate the reference of dac to form a output voltage droop proportional to the load current. the droop or so call ?active voltage positioning? can reduce the output voltage ripple at load transient and the lc filter size. fault detection the chip detects v core for over voltage and power good detection. the ?hiccup mode? operation of over current protection is adopted to reduce the short circuit current. the in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. application circuit setting mosfet driver detection and converter start up RT9241A/b interface with companion mosfet driver (like rt9600 or hip660x series) for correct converter initialization. the tri-phase pwm output (high, low, high impedance) pins sense the interface voltage at ic por acts (both v dd and v dvd trip). the channel is enabled if the pin voltage is 1.2v less than v dd . please tie the both pwm output to driver input for correct converter start-up. current sensing setting RT9241A/b senses the current of low side mosfet in each synchronous rectifier when it is conducting for channel current balance and droop tuning. the differential sensing gm amplifier converts the voltage on the sense component (can be a sense resistor or the r ds(on) of the low side mosfet) to current signal into internal circuit (see fig.1). fig.1 current sense circuit sample & hold gm to current balance to droop tune to over current detection 2/3 i x 2/3 i x 2/3 i x i x + _ i bp i bn r sp r sn r s i l isp x isn x sample & hold gm to current balance to droop tune to over current detection 2/3 i x 2/3 i x 2/3 i x i x + _ + _ i bp i bn r sp r sn r s i l isp x isn x
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 11 the sensing circuit gets i x = by local feedback. r sp = r sn to cancel the voltage drop caused by gm amplifier input bias current. i x is sampled and held just before low side mosfet turns off (see fig.2). therefore, , , t s , for switching period = t s fig. 2 inductor current and pwm signal droop tuning the s/h current signals from power channels are injected to adj pin to create droop voltage. the dac output voltage decreases by v adj to form the vcore load droop(see fig.3). protection and ss function for ovp, the RT9241A/b detects the v core by v sen pin. eliminate the parasitic delay and noise influence on the pcb path for fast and accurate detection. the trip point of ovp is 120% of normal output level. the pwm outputs are pulled low to turn on the low side mosfet and turn off the high side mosfet of the synchronous rectifier at ov p. the ovp latch can only be reset by v dd or v dvd restart power on reset sequence. the pgood detection trip point of v core is 8% out of the normal level. the pgood open drain output pulls low when v ocre exceeds the range. soft start circuit generates a ramp voltage by charging external capacitor with 10ua current after ic por acts. the pwm pulse width and v core are clamped by the rising ramp to reduce the in-rush current and protect the power components. ocp is triggered if one channel s/h current signal i x > 75 a. controller forces pwm output latched at high impedance to turn off both high and low side mosfet in the power stage and initial the hiccup mode protection. the ss pin voltage is pulled low with a 10 a current after it is less than 90% v dd . the converter restarts after ss pin voltage < 0.2v. three times of ocp disable the converter and only release the latch by por acts (see fig.4). fig. 4 fig. 3 droop tune circuit sp s l r r i sp s ) h / s ( l ) h / s ( x r r i i = 2 t l v i i off o ) avg ( l ) h / s ( l ? = v v v t in o in off ? ? ? ? ? ? = = x adj adj i 3 2 r v 0a 0v 2v 4v t0t1 t2 t3t4 time count = 1 count = 2 count = 3 overload applied ss v core i l falling slope = v o /l i l i l (s/h) i l (avg) pwm signal & high side mosfet gate signal low side mosfet gate signal inductor current sp s in o in o ) a vg ( l ) h / s ( x r r l 2 t s v v v v i i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? + _ ea i x fb comp v dac -v adj + _ v dac v adj adj r adj 2/3 i x1 2/3 i x2 + _ ea + _ + _ ea i x i x fb comp v dac -v adj + _ v dac v adj adj r adj 2/3 i x1 2/3 i x2
RT9241A/b www.richtek.com ds9241ab-01 october 2002 12 two-phase converter and components function grouping design procedure suggestion voltage loop setting a. output filter pole and zero (inductor, output capacitor value & esr) b. error amplifier compensation network current loop setting a. over current protection trip point setting by gm amplifier s/h current(current sense component ron, ispx & isnx pin exte rnal resistor value, keep ispx current = 75 a at ocp condition) vrm load line setting a. droop amplitude (adj pin resistor) b. no load offset (additional resistor in compensation network) power sequence & ss dvd pin external resistor and ss pin capacitor pcb layout a. kelvin sense for current sense gm amplifier input b. refer to layout guide for other item comp fb adj gnd vsen dvd ss isn2 isn1 isp2 pwm2 pwm1 isp1 vdd RT9241A/b +5v 12v vid 12v +v core pwm pvcc vcc boot ugate phase lgate gnd rt9600 12v pwm pvcc vcc boot ugate phase lgate gnd rt9600 compensation & offset droop setting driver power uvlo current sense components comp fb adj gnd vsen dvd ss isn2 isn1 isp2 pwm2 pwm1 isp1 vdd RT9241A/b +5v 12v vid 12v +v core pwm pvcc vcc boot ugate phase lgate gnd rt9600 12v pwm pvcc vcc boot ugate phase lgate gnd rt9600 compensation & offset droop setting driver power uvlo current sense components
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 13 khz 2 . 1 lc 2 1 = khz 8 . 8 cr 2 1 esr = 1 2 z c r 2 1 f = ) c c c c ( r 2 1 f 2 1 2 1 2 p + = design example for RT9241A two phase converter v core = 1.5v, v in = 12v, full load current = 40amp, droop voltage at full load = 120mv, ocp trip point for each power stage = 30amp (at sample/hold), low side mosfet r ds(on) = 6m ? at room temperature, l = 2 h, c out = 9000 f, capacitor esr = 2m ? . 1. compensation setting a. modulator gain, pole and zero modulator gain = saw-tooth wave amplitude v ramp = 1.7v, modulator gain = 8.6 = 18.7db lc filter pole = , esr zero = b. ea compensation network use type 2 compensation scheme (see fig. 5), , , mid-band gain = . choose r 1 = 2.4k ? , r 2 = 24k ? , c 1 = 6.6nf, c 2 = 33pf, get f z = 1khz, fp = 200khz, mid-band gain=10=20db, modulator asymptotic bode plot of ea compensation and pwm loop gain bode shown as fig. 6. fig. 5 ea compensation network fig. 6 asymptotic bode plot of pwm loop gain 2. over current protection setting ocp trip point current = 30a (at sample/hold) , r isp = 2.4k ? take the temperature rising for consideration, if mosfet working temperature=70 c and the temperature coefficient =5000ppm/ c, r isp (70 c) = r isp (27 c) {r ds(on) (70 c)/r ds(on) (27 c)} = 1.75k ? 3. droop setting full load current of each power channel = 40a/2 = 20amp, the ripple current = ? i l = , load current at s/h = , gm amp s/h , r isp = r isn = 2.4k ? , i x(max) = 46 a, required droop = 120mv = 46 a 2 2/3 r adj r adj = 1.97k ? . take the temperature rising for consideration, we just modify r isp like ocp setting. 4. ss capacitor c ss = 0.1 f is the suitable value for most application. ramp in v v 1 2 r r asymptotic bode plot of pwm loop gain -60 -40 -20 0 20 40 60 80 100 10 100 1000 10000 100000 1000000 10000000 frequency (hz) gain (db) 10 100 1k 10k 100k 1m 10m uncompensated ea gain compensated ea gain modulator gain pwm loop gain a 28 . 3 v 12 v 5 . 1 1 h 2 v 5 . 1 s 5 = ? ? ? ? ? ? ? a 36 . 18 2 i a 20 l = ? ? isp ) on ( ds ) max ( x r a 36 . 18 r i = + _ ea c 1 c 3 c 2 r 2 r 3 r 1 fb dacout v core comp r 3 , c 3 are used in type 3 compensation scheme (left nc in type 2) r ol r ol for no load offset setting a 75 r a 30 r i sp ) on ( ds x = =
RT9241A/b www.richtek.com ds9241ab-01 october 2002 14 layout guide layout guide place the high-power switching components first, and separate them from sensitive nodes. 1. most critical path: the current sense circuit is the most sensitive part of the converter. the current sense resistors tied to isp1,2 and isn1,2, should be located not more than 0.5 inch from the ic and away from the noise switching nodes. the pcb trace of sense nodes should be parallel and as short as possible. kelvin connection of the sense component (additional sense resistor or mosfet r ds(on) ) ensures the accurate stable current sensing. no kelvin sense, no guarantee for stable operation! switching ripple current path: a. input capacitor to high side mosfet b. low side mosfet to output capacitor c. the return path of input and output capacitor d. separate the power and signal gnd e. the switching nodes(the connection node of high/low side mosfet and inductor) is the most noisy points. keep them away from sensitive small-signal node. f. reduce parasitic r, l by minimum length, enough copper thickness and avoiding of via. 2. mosfet driver should be close to mosfet 4.the compensation, bypass and other function setting components should be near the ic and away from the noisy power path. v sw1 l1 sw2 l2 r in v in c in v out c ou t r l fig.7 power stage ripple current path
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 15 fig.8 layout consideration vcc comp fb vsen RT9241A/b pwm adj isn x isp x rt9600 vcc pvcc phase c boot c in l o1 v core c out c bp +5v in c c1 r c r fb r isn locate next to fb pin next to ic pin(s) locate near transistor use individual metal runs for each channel to help isolate output stages r isp locate next to ic parallel trace kelvin sense +12v or +5v next to ic pin(s) c bp +12v c c2 vcc comp fb vsen vcc comp fb vsen RT9241A/b pwm adj isn x isp x rt9600 vcc pvcc phase c boot c in l o1 v core c out c bp +5v in c c1 r c r fb r isn locate next to fb pin next to ic pin(s) locate near transistor use individual metal runs for each channel to help isolate output stages r isp locate next to ic parallel trace kelvin sense +12v or +5v next to ic pin(s) c bp +12v c c2
RT9241A/b www.richtek.com ds9241ab-01 october 2002 16 package information dimensions in millimeters dimensions in inches symbol min max min max a 12.598 13.005 0.496 0.512 b 7.391 7.595 0.291 0.299 c 2.362 2.642 0.093 0.104 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.229 0.330 0.009 0.013 i 0.102 0.305 0.004 0.012 j 10.008 10.643 0.394 0.419 m 0.381 1.270 0.015 0.050 20?lead sop plastic package m h b j b a c i fd
RT9241A/b ds9241ab-01 october 2002 www.richtek.com 17
RT9241A/b www.richtek.com ds9241ab-01 october 2002 18 richtek technology corp. headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corp. taipei office (marketing) 8f-1, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com

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